| 发布日期：2005/7/26
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浏览人数：174 |
| 有效期限：一个月
|
招聘对象：全职 |
| 工作地点：北京 |
招聘人数：不限
招聘内容：Requirements:
- Degree or above in Electronics Engineering;
- Sound Knowledge in VERILOG HDL;
- Previous logic design or using CAD tools (Cadence/Synopsys) experience;
- Independent, initiative and be able to work closely with others;
- Minimum 2-3 years experience in related field.
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工程师 （单片机设计）(不限)